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5G/IoT/Automotive
New Generations of Wireless and Their Impact on Measurement
With years of 5G deployment still to go and the vision for 5G still far from being realized, we are now engaged in serious dialogue for 6G. This may appear premature to many, but the time required to develop a new generation of mobile communications drives the discussion to start fifteen years before the vision can coalesce into its first practical manifestations. 5G set the stage for building a user-centric vision of what mobile communications could be. The early discussions of 6G have a similar ring: how will it appear to the user or the business or the government who will be putting this technology to use. Niels Bohr said that “Prediction is very difficult, especially if it is about the future.” But that will not stop us from anticipating the future. My prediction is that the new technologies, much like their predecessors, will have to be tested and validated. The last two generations have taught us that this goes well beyond measuring bit error rates, RF power levels, modulation accuracy, and even data throughput. A system that is designed to accommodate ever more complex and demanding use-models needs not only for its technologies to be tested, but also its end-to-end functionality and performance to be validated. Our industries and society will move from seeing mobile communications as a novelty and luxury to seeing it and using it as integral part of society, government, and business. This will drive the requirements for measurable service assurance and performance to evolve from adherence to a standard to adherence to SLA and to policy. What demands will standards and policy-makers place on things like “Holographic Type Communications”, “Multi-sense Networking”, and “Time-Engineered Applications”? How will we know if these behave as expected, or as promised, especially as mobile communications migrates to “Critical Infrastructure”? This presentation is an exploration of how such validation has evolved over the past five generations, what is in store for 5G, and how this will have to change for 6G.
The Latest Trends in 5G: Market Update and Forecast, Deployment Status and Technology Advances
The continued rise of 5G commercial networks in 2020 is seeing some impressive results. With the impact of Coronavirus now manageable, network densification with small cell deployments, spectrum availability, and 5G device launches are driving the commercial landscape. The move to 5G standalone network deployments continues to march ahead, as new radio access and core network technologies transform the wireless network landscape. Enterprise 5G solutions begin to emerge with new developments in specific use cases across a variety of different industry verticals.
Chris Pearson, President of 5G Americas, will cover a broad range of topics including the overall market impact for network operators and equipment manufacturers, growth in 5G network deployments and subscribers, opportunities in new industry sectors, and advances in technologies like dynamic spectrum sharing, open RAN, massive MIMO and beamforming. In addition, he will cover in detail the low, mid and high band spectrum challenges and opportunities across the Americas. What’s next for 5G and beyond?
Chris Pearson, President of 5G Americas, will cover a broad range of topics including the overall market impact for network operators and equipment manufacturers, growth in 5G network deployments and subscribers, opportunities in new industry sectors, and advances in technologies like dynamic spectrum sharing, open RAN, massive MIMO and beamforming. In addition, he will cover in detail the low, mid and high band spectrum challenges and opportunities across the Americas. What’s next for 5G and beyond?
WiFi 6E Chipset Characterization
The session will include an overview of the Doherty topology and its underlying principles of operation. It will describe the design of a fully integrated Doherty MMIC for the 3.5 GHz frequency band using the 0.4 µm GaN-on-SiC device. Details of the MMIC design, layout and packaging will be described. The measured performance shows good agreement with simulated and clearly demonstrates the advantage of the Doherty architecture.
The packaged MMIC was assembled onto a representative PCB for evaluation and achieved a PSAT of 45 dBm with a peak PAE of 50%. The PAE at 8 dB power back-off was 31.5%. Using a 100 MHz 5G NR signal with 11.5 dB PAPR the EVM was 3.5% and ACLR was less than -33 dBc at 36 dBm (4W) average power.
The Next Generation of EM Analysis, Beowulf, from Sonnet
Since 2014, Sonnet has been hard at work on a commercial implementation of the Unified-FFT algorithm. The result is an upcoming product named Beowulf, after for the Old English Poem. Like the titular character of the poem, the Beowulf solver has a knack for solving monstrously large problems. Scaling as O(N log N), Beowulf uses a complex and unique FFT solution to calculate full-numerical precision solutions for large problems, all with a fraction of the time and memory requirements of conventional solvers. Sonnet is proud to perform a live demonstration with a pre-release version of the solver.
Characterizing, Troubleshooting & Mitigating Wireless and IoT Self-Generated EMI
It is fairly common to find multiple on-board sources of energy causing EMI on today’s portable, mobile, and IoT devices. The EMI from these energy sources can couple and often interferes with the receiver performance of cellular, GPS and other wireless modules. This presentation describes methods for identifying, characterizing and reducing the coupling from these energy sources.
Doherty Power Amplifiers – Moving to mmWave
Doherty power amplifiers are widely used below 6 GHz to improve Power Added Efficiency (PAE) for communications applications. Designing Doherty PAs incurs many challenges, which increase as the frequency of operation moves towards mmWave. LDMOS, which is commonly used below 6GHz, cannot be used, and more integrated approaches need to be utilised to minimise parasitic inductances and capacitances. Recently, short gate-length GaN-on-SiC MMIC processes have become commercially available, opening up the possibility of realising medium power, high-efficiency Doherty power amplifiers at mmWave frequencies.
The design of a Doherty MMIC for the 28GHz 5G frequency band will be described. First pass design success was achieved using an asymmetrical topology designed on the commercially available 0.15µm G28v5 GaN-on-SiC process from Wolfspeed. The MMIC was packaged in a cost-effective, compact 4x4mm QFN package. Details of the design, simulation, layout, and packaging will be described.
Resourceful RF Testing of Wi-Fi Devices using an AP/STA Simulator
Certain test instrument features can make testing more efficient than ever before. In this workshop, learn how to simulate an actual Wi-Fi Access Point or Station to conduct RF transmitter and receiver tests on devices that support Wi-Fi 1 up to version 6. Benchmark RF performance of your Wi-Fi device, or a competitor’s, under real, live network connection and mitigate problems such as USB noise, dropped connections and more.
Digital Transformation with 5G, Edge Compute and AI
As we transition from 5G buzz to 5G reality, it is getting unequivocally certain that 5G is not just the next generation wireless connectivity, but it is much more than that. Per ABI research, by 2035, the 5G industry value chain will be worth $3.5 trillion. With its distinguishing characteristics like Enhanced Mobile Broad Band (EMBB), Machine-to-Machine Communication (MMTC), and Ultra reliable Low Latency Communication (URLLC), 5G will create opportunities we have never thought possible, especially in time-sensitive and mission-critical operations. Based on the recent Gartner research, more than 40% of the data will be created and analyzed at the edge of the network by 2025. 5G, when coupled with edge compute and artificial intelligence, brings value across variety of enterprise/IoT use cases, specifically in the areas with low latency and real-time applications need such as autonomous driving, smart manufacturing, digital security and surveillance, real-time gaming, high frequency financial transactions, etc. COVID-19 impact to world economy and day-to-day life is further emphasizing the importance of 5G and Edge compute with the rise of requirements in areas such as remote medicine/diagnosis, remote education, social distancing monitoring, etc. and will make 5G an ubiquitous reality sooner than everyone predicted.
How 5G Is Expanding Into Manufacturing and Automotive to Bring Increased Efficiencies and Safety
This session will cover how new capabilities in 5G such as ultra- reliability, direct communication and overall enhanced performance will expand 5G into new verticals including industrial manufacturing and automotive. For example, with 5G’s capabilities, manufacturers can create smart factories where the wired industrial Ethernet is replaced with wireless 5G communication to make it possible to quickly reconfigure the production line and ultimately increase efficiency. These new use cases can be served with so called 5G private networks, which is a local 5G network that is dedicated and optimized for a specific purpose, which provide the owner full control over both the performance as well as the data. Meanwhile, the capabilities of automotive vehicles will change forever with 5G’s enabling of cellular vehicle-to-everything (C-V2X), which also includes the capability of two vehicles to communicate directly with each other independent of a cellular network. This new capability called the C-V2X sidelink effectively brings a new sensor to automotive safety, for example for collision avoidance. With C-V2X, automotive manufacturers will be able to offer superior communication range, reliability, cost-efficiency, and safety.
Getting to the Source: Integrated Circuits (ICs) and Component EMC Testing
Failures in EMC testing often result in treating the symptoms of the issue rather than attacking the source. If we know the source of the issue rather than chase the symptoms, we will save time, cost, and frustrations. In this discussion, we will attack EMC testing from a component standpoint so that when issues arise, we can pinpoint the solution, saving time, cost, and frustrations.
Filtering mmW Frequencies with LTCC Technology
As more commercial applications gravitate toward mmWave frequency bands (30 to 300 GHz), an increasingly crowded RF spectrum will require some adaptation of legacy technologies. In particular, the approaching rollout of fifth generation (5G) wireless up to 40 GHz and beyond, as well as a growing number of Satcom systems in the Ka band (26 GHz to 40 GHz) means that these industries will face similar challenges: Legacy technologies using lumped elements or waveguides have not yet provided a high performance, low cost and physically compact solution for mmWave frequencies.
In recent years, Mini-Circuits has invested heavily in developing its product lines to support wider bandwidths at higher frequencies in response to growing demand for solutions in the mmWave range. New development in the LTCC product line has been one area of notable progress. Using an iterative, multi-physics simulation approach, combined with feedback from extensive prototype manufacturing of test samples, Mini-Circuits has developed a high-confidence design approach for first spin success of new LTCC products up to 50 GHz.
With an LTCC portfolio of over 700 commercially available products, including filters, couplers, splitters and baluns, Mini-Circuits has now developed a family of products to address the 5G FR2 mmWave and SatCom opportunities.
This workshop will explore how Mini-Circuits’ latest LTCC filter products address the challenges faced by the industry for applications in the mmWave bands. New catalog releases will be discussed along with compelling test results for products in development.
Material Measurements with VNAs
The increasing popularity of mobile communications, wireless data transfers, and instant access technologies is giving rise to the need for faster data rates and more data channels to support an ever-increasing number of users and their devices. To meet these demands, circuits must be made smaller and perform faster than ever before. One way manufacturers accomplish this is by leveraging materials that have good dielectric properties (complex permittivity) in the components and devices used to build these circuits (e.g., FR 4 and RF Duroid among others). Another way is to design these components and devices at higher frequency ranges where more bandwidth is available to transfer data more efficiently. However, while manufacturers are quoting good permittivity of the existing materials at low frequencies, these same solutions may not be adequate for designing high-frequency RF and microwave applications. This workshop will examine the issues component and device manufacturers and their engineers will face when designing their solutions in higher frequencies.
PCB/Interconnect Design
Stretching the Limits of PCB Design
Expanding markets, such as automotive, IoT, wearables, and healthcare, continue to drive innovation in printed circuit board and interconnect design. While new materials and technologies are being stretched to their limits, some fascinating new design and manufacturing methods are offering completely new ways to create PCBs, eliminating some of the old trade offs and revealing new ones. In this keynote, the editors of Microwave Journal and Signal Integrity Journal take a closer look at some of the market drivers, creative new products, and new ways of manufacturing PCBs. The keynote includes interviews with leaders from two companies developing new capabilities: Dr. Jaim Nulman, Nano Dimension CTO, discussing 3D printed PCBs and Philip Johnston, CEO of Trackwise Designs plc. discussing infinitely long, flexible PCBs. Join us in this keynote for a fascinating and engaging journey into what’s possible.
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Bridging the Gap to 112 Gbps PAM4 – The Benefits of TwinAx Cabling
As data rates scale to 112 Gbps and beyond, twin-axial cabling is becoming a vital part of system architecture and design. This session explores the numerous twin-ax construction options available and their signal integrity advantages and challenges.
How to Characterize PCB Materials to 50 GHz
Characterizing PCB materials for Dk and Df of the dielectric materials, as well as the surface roughness can be challenging. A typical build will often have core and pre-preg materials with Dks that can vary by 10-15%. For low loss materials with Dfs less than 0.005, extraction of Df can be difficult. Further, separating the dielectric loss from the surface roughness loss adds to the complexity of characterizing the losses. This presentation will give examples of different behaviors in the S-parameters and single-bit response of materials for loss, and multiple Dks. Then an approach for characterizing the materials will be presented.
RF Millimeter-Wave PCB Design Considerations for High Speed Digital
As High Speed Digital (HSD) rates are increasing, there are more electrical performance properties related to RF technology which need to be considered by the HSD designer. As a basic comparison, RF technology is focused on frequency domain and HSD technology is focused on time domain. Some electrical performance concerns in frequency domain can impact the time domain performance of HSD signals and some of these concerns will not. However the larger concern for the potential impact is likely related to the increase in channel speeds of 56Gbps and above
The clock signal used in HSD to generate a digital pulse train, is basically a composite of multiple RF waves which include some signal processing. The lowest frequency wave is the Nyquist frequency and the other waves that make up the building blocks for the clock signal are 3rd, 5th and 7th harmonics. The actual HSD processing nowadays is more complicated, but these basic relationships will be explored in this paper when comparing electrical performance of RF circuits and HSD circuits at high frequencies and rates. Comparisons will be made with single ended and differential pair circuits at frequencies up to 110 GHz and HSD rates up to 112 Gbps.
Demystifying PCB Transmission Line Interconnect Modeling for High-level Design
During the high-level design stages for new a project, board designers are often overwhelmed when trying to choose appropriate diff pair geometry, board material, and stackup to meet high-speed serial link loss budgets. Part of the printed circuit board (PCB) interconnect challenge is modeling transmission lines accurately. Although many EDA tools include the latest and greatest models for conductor surface roughness and wide-band dielectric properties, obtaining the right parameters to feed the models is always a challenge. So how do we get these parameters? Often the only sources are from data sheets. In most cases the numbers do not translate directly into parameters needed for these tools. By using dielectric material properties, copper foil and oxide alternative roughness parameters from data sheets, a practical method of modeling high-speed PCB interconnect is presented.
PC Board and Interconnect Design for Low EMI
As a consultant for over 10 years, I’ve realized the root cause of many design issues revolves around the circuit board design and how the I/O and power connectors are arranged and filtered. Poor board designs and poor interconnect placement and filtering can result in radiated emissions, radiated immunity, and electrostatic discharge (ESD) compliance failures, among others. Bad designs often result in endless cycles of trial and error mitigation, compliance testing and board spins. This drags out the schedule and is very costly. In the presentation, I’ll explain how digital signals propagate in boards as electromagnetic fields. I’ll also explain how interconnect placement and poor filtering design and layout can affect the EMI performance. Once you understand this, then board stack-up, trace routing, filter design and interconnect placement should become very clear and you should be able to design a low-EMI board the first time!
Exploring Power Dissipation Thermal Ratings for Fixed Attenuators
A number of thermal/power design challenges are found when PCB Designers evaluate the use of fixed attenuators.
It is helpful to explore and understand relationships of applied power, dissipated power and the factors involved across multiple dB values of attenuators whether fixed in a component network or created using discrete individual resistors on a PCB.
Understanding all factors involved with properly rating attenuators offers a useful insight into practical challenges. Further, understanding the best practices on how to self-evaluate applications and apply them to the components required to realize designs becomes even more beneficial to designers. Some factors explored here include, termination style, pad and via sizing, operating temperature, component substrate, resistor size, trim style and tolerance as they relate to power/thermal performance. Some insights into balancing RF and power performance will also be explored.
High Performance Laminates for Multigigabit Applications
This short talk will look at the requirements of multigigabit signaling as related to the PCB materials available with which to fabricate these PCBs. It will draw on the more than a dozen test PCBs fabricated for the purpose of evaluating these laminates. Included will be some comparisons of laminates currently used to fabricate these PCBs.
Principles of Designing the Board Stackup for Electronics and Manufacturability
The designer MUST be involved in the decision making for a board stackup, as the fabricator only knows his own needs, not the needs of the signals. The stack affects the way the signals flow and so can affect many electronic aspects of the functioning circuit like layer count, field spread/interference, return current, impedance control, and layer paired routing. Likewise, if the stack is not set up correctly, it will affect whether the board might warp, have a higher cost, or whether it will meet standards. In today’s higher speed designs it is critical to do this step well, so we will discuss the issues that are needed for a good stackup, both from an electronic and a manufacturability perspective.
Developing Wireless PCB Applications with EM Verification and an RF Design Flow
Today’s PCB designers face multiple challenges incorporating RF/microwave, analog, and digital design elements together on the same PCB. To successfully integrate RF/microwave content and mixed-signal designs, PCB layout tools and RF circuit design software must exchange design data efficiently.
This workshop will address two aspects to successful RF PCB design, namely EM verification as well as RF/microwave IP creation. The Cadence® software platforms of Allegro® and AWR® will be showcases through several practical, real-world examples that demonstrate the need for a close link between RF circuit/EM co-design and enterprise-level manufacturing layout tools.
Signal Integrity/Power Integrity
Real World 112 Gbps PAM4 System Architectures
As 112 Gbps PAM4 data rates become reality, developers are challenged with balancing increasing throughput, scalability and density demands with concerns such as power consumption, signal integrity, cost and time-to-market. In this keynote, Samtec will demonstrate real-world solutions from front-panel to mid-board, mid-board to backplane, high-performance test and on-package system architectures that exceed the demands of next generation data transmission.
Circuit Modeling for High-Speed Communication in 5G, IoT, and SatCom Applications
The performance of microwave and millimeter-wave antennas and circuits plays a key role in the application area of 5G, the internet of things (IoT), and satellite communication. The evaluation of such devices before fabrication and testing through electromagnetics simulation tools is beneficial to reduce the time and effort required in the design process during the development cycle.
In this session, you will see a live demonstration in the COMSOL Multiphysics® software showing how to set up and run a simulation to design and evaluate a grounded coplanar waveguide (GCPW) line with edge launch connectors. We will investigate the impact on the performance, such as loss per unit length of the circuit board by choosing different types of surface roughness models. The live demo also introduces a fast and efficient modeling workflow for time-domain reflectometry (TDR) analysis using fast Fourier transformation.
A Holistic Power Integrity Approach Reduces Board Spins, Supports System Analysis and Reduces VRM Modeling Effort
I hear many recurring complaints from engineers attending my lectures. They can be summarized as:
- Continuously increased technology designs on a constant, short cycle
- Multilayer board spins are time consuming and expensive. Must be minimized
- Many key design parameters and guidelines are not provided by the semiconductor manufacturers or are inaccurate.
- Power electronics engineers rarely get involved in the troubleshooting or modifications caused by their designs. This effort mostly falls on the high-speed engineers.
- Far too many engineers are developing simulation models for free or inexpensive simulators. This costs valuable engineering time, without creating a net benefit to the system evaluation.
A simple design workflow could address many of these issues, resulting in more cost-effective designs with fewer expensive board spins.
The proposed workflow would also reduce the effort expended by semiconductor companies in developing simulation models.
The result is a unified, end-to-end model, providing power rail noise, spectral content, EMI, dynamic transient response and power rail impedance all within a single model. This approach also allows the analog, power, digital, RF and uWave models to all be incorporated into a single system level simulation model.
My Simulator Is a Soldering Iron: PDN Design Guidelines With an Homage to Bob Pease
We will explore the four most important design guidelines for the power distribution network using a simple prototype circuit in which we can actually measure the noise on the PDN, while we make interconnect changes and component changes. While we do not recommend designing your product by building it and testing, we can gain some design insights by seeing the impact on the actual noise from physical design changes we make in real time.
PAM-Fried Engineer’s Guide to Crosstalk, ISI, FEC, Equalization
In this talk, we’ll see how crosstalk, ISI (inter-symbol interference), FEC (forward error correction), and equalization have driven high speed IO away from NRZ (which should be PAM2–2-level pulse amplitude modulation) to the madness of PAM4, PAM5, PAM6, PAM-fried engineers. Along the way, we’ll investigate how simple, righteous design constraints have evolved to arbitrarily complicated figures of merit like malicious COM (channel operating margin) and evil ERL (effective return loss) by standards committees intent on world domination. It’s a sad tale, guaranteed to keep engineers employed.
DDR4-3200 Channel Modeling and Signal Integrity Analysis Using an FPGA
DDR4 requires tight specifications for high-speed operation, and then to ensure design margins against a target system bit error rate of 1e-16. DDR4 is now able to reach speeds of 3200 Mbps per pin with an FPGA as the memory controller. This talk shows how to model a DDR4 memory channel with an FPGA and demonstrates DDR4 channel and signal integrity analysis for DDR4-3200 speeds. We consider channel characteristics, on-die terminations choices, and equalization controls to optimize our DDR4 signals. The talk includes preliminary analysis that provides channel simulations using Keysight Pathware ADS with the Xilinx Versal FPGA with MICRON memory.
System Oriented Testing for Memory Interfaces
Next-generation data center and server architectures rely heavily on high-speed signaling interfaces. No longer restricted to the networking sub-systems of the data center, these high-speed interfaces are used to connect processors, AI hardware accelerators, switching and routing fabrics, and of course extremely high-density memory channels. Testing these highly parallel signaling interfaces represents a particular challenge due to the tight interaction between environmental parameters, physical layer effects, and protocol payloads. Memory test solutions in particular must be capable of adapting to protocol changes and in-depth compliance measurements, as well as providing a means to perform system-level functional validation. This workshop will include an overview and demo of Introspect’s highly parallel memory interface test solution, showing the role it plays in ensuring the proper characterization and screening of DIMMs and components for the DDR5, and similar, memory standards.
Improve Power Integrity With Decoupling Solutions
A typical PCB high-speed digital design application can have tens to hundreds of decoupling capacitors for a high-speed power domain, in order to achieve a specified target impedance. Design choices for applying the decoupling capacitors include where to place them, how to connect them, what values to use, and how many to use. This presentation will give a brief overview of the inductance contributions of each part of the current path from the decoupling capacitors to the IC package, and how each piece of the inductance is related to the power distribution network impedance. Then a systematic approach for developing a decoupling solution addressing the typical design choices will be presented.
Bending Electromagnetic Simulation Tools to Your Will – How to Design 112 Gbps Systems Every Times
There is an art and science to utilizing an electromagnetic modeling tool to analyze and optimize designs and obtain reasonable answers consistently. Session attendees will learn how to “trick” a tool into providing the most accurate insight possible for a design. We’ll talk about setup, ports, boundary conditions and other tricks of the trade that help derive the best results from EM Tools. We’ll also discuss quick ways to obtain approximate answers that will help engineers maximize their efficiency.
Using TDR to Solve Signal Integrity Issues
Gone are the days where only basic voltage and timing measurements would suffice for validating a high-speed design. Large-scale design integration with devices such as SoCs or FPGA require strict impedance control, tight timing references and a host of other complex parameters to manage. How do you efficiently address signal integrity issues? Where do you start debugging? In this talk, you will learn about new tools that can help you be more efficient at debugging signal integrity issues.
Update Your SI / PI Design and Analysis Methodology for DDR and GDDR Memory Interfaces
Memory interfaces continue to be the biggest challenge for signal and power integrity teams. Simultaneous switching of single-ended signals at the speeds of serial links take this design challenge to a new level over the well-behaved differential pairs of peripheral component interconnect express (PCI Express). With voltage swings below one volt for the low-power versions of these interfaces, there is no longer any margin for power ripple. Design teams need a robust and proven methodology to address these challenges to ensure designs come up and work in the lab the first time.
Using the fifth version of the double data rate interface (DDR5) and the sixth version of the graphics double data rate interface (GDDR6) as examples, this workshop presents work that can be done before layout, during layout, and how to both accelerate and minimize the number of post-route re-spins due to powerful, yet memory efficient signoff simulation tools.
Radar/Antennas
Advancements in Phase-Related Measurements for Radar Applications
In this session, we will give an overview of the three topics regarding the phase of a radar signal in the widest sense. We will start by presenting an easy approach for measuring the stability of pulsed signals and then talk about the generation of multi-port phase-coherent signals needed to simulate an angle of arrival (AoA) scenario. For the automotive sector, it will be shown how to use a compact antenna test range (CATR) anechoic chamber and a high-end oscilloscope to measure phase-coded radar signals.
Radar Signal Analysis
Design, verification, troubleshooting and maintenance of radars has never been more demanding. Proper design and operation is critical to the safety and security of aviation. To reduce the possibility of a catastrophic event, aviation safety standards require transponders to undergo periodic maintenance and calibration. As a result, engineers and technicians have a need for the best analysis tools available whenever and wherever required. In addition, they want to be certain of the measurements they make. All this needs to be done in less time with less money.
Recent Radar Advances and Market Trends
The radar enterprise is experiencing significant growth and change in both government and commercial sectors. Military radars are continuing to evolve ever more sophisticated capabilities such as waveform agility/adaptivity, advanced high-power operation, and new cognitive operating capabilities. Moreover, this is a major thrust in developing radars and other RF systems specifically for unmanned aerial systems (UAS) that places a premium on low cost, size, weight and power (C-SWAP). The commercial sector is likewise experiencing significant growth in similar areas in the automotive and UAS detection and tracking industries. Indeed, the first cognitive radar for automotive applications was just announced in 2019. This talk will provide an up to date overview of these recent trends with a contemplation on what’s in store for the future. Specific topics include:
- Cognitive radar
- Advanced waveform adaptivity/agility
- MIMO radar advances
- Low C-SWAP radars
- Advanced embedded computing and signal processing
Metamaterial Electronically Steering Antennas: Enabling High-Performance Radar in the Age of Autonomy
Electronic beam-steering phased-array antennas (ESA’s) are the gold-standard of performance in radar and communications. Unfortunately, there are longstanding challenges to realizing low-cost phased-arrays, and as a result many applications have to make-due with lower-performing antennas. Recently, new antenna architectures leveraging dense metamaterial design are changing that, offering high-performance ESA’s at breakthrough cost, which is in turn revolutionizing a number of markets. We will introduce the basics of the metamaterial design approach, and look at applications and techniques Metamaterial ESA’s are unlocking.
Metamaterial-based Miniaturized Antenna Designs for Ultra-Wide Band Applications
In modern communication systems the demand for miniaturization and integration of multiple radio systems such as communication system, GPS receivers, 5G, wireless Internet devices operating at multiple frequencies are increasing. These systems using cognitive radio or flexible radio need smaller wideband antennas. The antennas based on metamaterial structures such as high permittivity periodic structures, mushroom, EBG, FSS, composite left/right-handed etc. are capable of greatly improving antenna performance. The use of metamaterials in antenna design not only significantly reduces the size of the antenna but also improve other antenna parameters such as increasing gain, enhancing bandwidth, or generating multiband frequencies of antennas operation. EBG structures which exhibit metamaterial behavior, are used intensively in the application of microstrip antennas. These structures are adopted to reduce surface waves and increase the gain of antennas and it was first introduced as frequency selective surfaces (FSS). This webinar will explain the latest research and development of metamaterials-based antenna technologies for ultra-wide band applications.
Latest Trends and Technology in Phased Arrays
Phased arrays have traditionally been used for military radar systems. While this remains a significant and growing use for phased arrays, new applications have emerged. In fact, phased arrays are being used or planned for use on a wide range of systems such as 5G, satellite communication, and ground stations. As a result, significant investment has occurred in developing innovative phased array solutions. In this talk, Dr. Sturdivant will describe phased arrays, their key features, solutions, and latest innovations being developed.
Interactive Radar: Algorithmic Perspective
Radar has evolved from a complex, high-end aerospace technology into a relatively simple, low end solution penetrating industrial, automotive and consumer market segments. This rapid evolution has been driven by two main factors: advancements in silicon and packaging technology that has led to miniaturization, and growth of computing power that has enabled the use of deep learning algorithms to tap the full potential of radar signals. Radar sensing has enabled several interactive human-machine interface applications and its application continues to grow multi-fold in recent years. For adoption of short-range radars for several industrial, consumer and in-cabin automotive applications require reliable system performance at small form factor, low-power and low-cost.
To enable interactive radar sensing applications advanced signal processing and deep learning algorithms are required that can parse the radar return echo into meaningful target information or understanding the user’s intent. In this talk, we demonstrate and highlight how radar processing are enabling two interactive applications, namely gesture sensing and human localization & tracking, which finds use in several advanced industrial, consumer and in-cabin applications.
Additive Manufacturing for RF and Microwave Devices
There is growing need to adopt additive technologies for the production of RF/microwave electronics. This trend is motivated by the need for rapid prototyping and the production of RF systems that are flexible, lightweight, conformable and wearable. Printing RF electronics for DoD applications (e.g., radars, communication systems) is challenging since the requisite materials, components and systems demand higher performance than required for low frequency applications.
This talk will describe several printed devices and subsystems, including tunable frequency selective surfaces, phased arrays, printed phase shifters, and printed varactors. Ink development, hybrid chip integration, printed interconnects, and additive microelectronic packaging are key elements of this research. Our work includes multi-physics based design and modeling as well as the development of printing/processing technologies. The formulation of new materials (inks etc), and characterization of their properties at microwave frequencies, are key challenges in applying additive manufacturing to printed RF and microwave devices. Details of these challenges and ways of mitigating them through specific applications, which exemplify all stages of development, will be presented. Details of a novel ferroelectric ink, tunable substrates, printed interconnects, and novel ink characterization methods, the key enablers for these applications and devices, will be described.