April 24: PCB/Interconnect/EMC-EMI Sessions
May 22: 5G-6G/Wi-Fi/IoT Sessions
October 23: Radar/Automotive/SATCOM Sessions
PCB/Interconnect/EMC-EMI – April 24, 2024
10:00 a.m. – 10:30 a.m. Eastern Time
KEYNOTE: The Road from 1Gbps-NRZ to 224Gbps-PAM4
Augusto Panella
Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR capability of the chips.
As we move through the speed grades, the physical layer design of PCBs, cables assemblies, and connectors evolves. The latest data throughput and latency-driven signaling updates challenge previously acceptable design trade-offs. We’ll review interconnect design progression from 1Gbps transmission line data rates to the 224Gbps rates to highlight the on-going refinement of design goals.
10:30 a.m. – 11:00 a.m. Eastern Time
FEATURED TALK: How to Navigate Chiplet Design Complexities with Electronic Design Automation
Tim Wag-Lee
The massification of high-computational applications, such as Artificial Intelligence (AI), is steering the semiconductor industry from monolithic to chiplet-based design architectures. In this new design philosophy, various chip functions once housed within a single large die are now segregated into modular smaller dies, called chiplets, that can be combined in a larger system. Chiplets offer improved scalability, flexibility, and cost-effectiveness but pose new challenges, especially in terms of die-to-die (D2D) communication and system management. This presentation discusses the chiplet-based design workflow and how Electronic Design Automation (EDA) tools can help overcome these challenges.
11:00 a.m. – 11:30 a.m. Eastern Time
Visualization of PCB Via Breakouts for Layout and Crosstalk Control
Scott McMorrow
Signal integrity engineers are rarely skilled at the art of layout, often designing “optimized” via breakouts that are tough, if not impossible to route in a layout environment. On the other hand, layout artists are good at their craft of insuring that all signals are routed and meet manufacturing requirements, but rarely consider signal integrity requirements. Since signal integrity engineers often make the job of layout more difficult with their fancy designs, and humongous antipad openings, it is our responsibility to at least make the process less painful for all involved. This session shows how to use a free tool that can easily visualize via breakouts for arrays of high performance signals, so that several constraints are met simultaneously:
- Acceptable insertion loss, return loss and impedance control
- Acceptable routing ability in the layout preferred direction
- And the ability to enhance the design with additional crosstalk guarding ground vias
11:30 a.m. – 12:00 p.m. Eastern Time
Mitigating EMC Risks Early – Before the First Prototype
Marek Jableka and Gilad Shapira
EMC challenges are often uncovered late in product development, leading to major delays and expenses. Identifying EMC risks early is critical for companies today.
This presentation will explore modern EDA solutions that support the design process. Attendees will learn techniques to spot design choices prone to EMC issues without a prototype. Finding these risks early allows quick, low-cost mitigation. The focus will be on practical methods and tools usable by both electronics and layout designers in their daily workflows, without requiring deep EMC expertise. We’ll also prioritize solutions that yield rapid results.
We’ll demonstrate solutions for verifying schematics and harnessing the power of modern AI/ML-based analysis against component datasheets. Discover techniques to tackle EMC challenges in PCB design and delve into PCB verifications paired with a simulation-driven approach, unveiling strategies for addressing power and signal integrity concerns.
12:30 p.m. – 1:00 p.m. Eastern Time
Things Not Seen on the Schematic
Patrick G. André
With the best intentions to have a great design that will pass EMI testing, the results are at times disappointing. The reasons are often not well understood, and the solutions are a mystery. The reasons for this can be related to the parasitic issues of the components and layout. These issues and techniques on how to avoid them will be discussed.
1:00 p.m. – 1:30 p.m. Eastern Time
Near Field EMI Measurement & Simulation Correlation for Mixed Reality Rigid Flex Designs
Kundan Chand, Raul Stavoli and Pedro El Awar
One of the major design challenges for MR/VR devices is to meet electromagnetic interference and compatibility (EMI/EMC) standards while also implementing high density routing in small form factors. It is critical to capture these issues early in the design cycle to minimize design iterations and to have more flexibility with routing, component placement, etc. This workshop introduces a novel approach to modeling EMI/EMC analysis with a simulation flow that targets a system comprising complex packages (PKGs) and rigid-flex PCBs (RFPCs), which are designed for MR/VR applications. Using Cadence’s Clarity 3D Solver, near-field distribution caused by high-speed clock (CLK) signals will be extracted. The modeling includes cross-hatched planes, multiple stackups, and current excitations. In addition, the challenges faced while correlating EMI for various bending angles of the RFPC will be shared. Excellent correlation between simulated and measured data will be demonstrated when comparing the H-near fields in near-field tests. The presented EMI/EMC simulation flow will enable engineers to pinpoint potential EMI/EMC issues via the field propagation throughout the system and simplify the challenge of meeting EMI/EMC compliance for designers.
1:30 p.m. – 2:00 p.m. Eastern Time
Empowering Careers in Electronics: Navigating Interconnects and PCB’s
Tara Dunn
Uncover the pivotal role of networking and continuous education in the dynamic world of electronics interconnects and printed circuit boards (PCBs). Explore the profound impact of training initiatives on career advancement and job performance, emphasizing the need for professionals to leverage available educational opportunities. Understand the relationship between industry and workforce development, shedding light on how the flourishing electronics sector propels career growth and is attracting a new generation to electronics manufacturing. Addressing current industry trends, the talk will spotlight the top technical topics capturing attention. Join us to discover the keys to success in this rapidly evolving field.
5G-6G/Wi-Fi/IoT Sessions
10:00 a.m. – 10:30 a.m. Eastern Time
KEYNOTE: Towards an AI-native Air Interface for 6G
Andreas Roessler
Machine learning (ML) has achieved tremendous success in a wide range of applications, such as image and video recognition, object detection and natural language processing. Over the last few years, researchers and key industry players have been investigating the native support of AI/ML-based models and algorithms for signal processing in the future 6G air interface. The initial focus will be on the receiver part as the concept of a neural receiver is introduced. Simulations show a performance gain compared to traditional concepts, but open questions remain about computational complexity, power consumption and lifecycle management.
10:30 a.m. – 11:00 a.m. Eastern Time
FEATURED TALK: Multiphysics Modeling of High-Speed Communication Devices
Andrew Strikwerda
In this session, we will explore the use of the finite element method (FEM) for multiphysics modeling in high-speed communication technologies, such as phased antenna arrays and 5G millimeter-wave filters. The performance of microwave and millimeter-wave antennas and circuits is pivotal for 5G, the internet of things (IoT), and satellite communications. By employing electromagnetic simulation software to assess these devices before physical fabrication and testing, the design process can be streamlined significantly, saving both time and effort throughout the development cycle.
We will introduce an efficient modeling workflow for microwave and millimeter-wave devices and demonstrate how to incorporate additional physical phenomena such as electromagnetic heating. The session will conclude with a comprehensive overview of the advantages of multiphysics couplings that account for heating, mechanical deformations, and other physical effects.
11:00 a.m. – 11:30 a.m. Eastern Time
Key Insights from Ericsson Microwave Outlook
Mikael Öhberg
The introduction of 5G has seen E-band spread to most parts of the world, in this the 10th edition of the report, we see that the E-band spectrum fulfills the capacity needs for most deployments even beyond 2030. Driven by advancements in microwave technology, the antenna toolbox has expanded to provide diverse options and possibilities. Operational costs for managing a microwave network can be significantly reduced by applying network automation. To find out more about this and other interesting topics, download Ericsson Microwave Outlook 2023. In this year’s edition we continue providing insights and trends up until 2030 in the wireless backhaul industry.
11:30 a.m. – 12:00 p.m. Eastern Time
Solve RF Design Challenges to Achieve Low EVM with 5G Modulation
Daren McClearnon
Digitally modulated 5G signals demand wider bandwidth and higher linearity from RF transceiver circuits, which then require more advanced design techniques. However, many RF designers continue to design using only CW signal in their design software, which leads to ambiguity about the true design margin of their components, and the effectiveness of their design approaches. Error vector magnitude (EVM) has emerged as the key figure of merit for circuit design and optimization, going beyond traditional analog measures such as P1dB and IP3. It’s well known in measurement equipment, but how to apply it effectively and inexpensively in simulation, as a design tool?
This webinar will highlight a variety of practical simulation techniques for not only creating realistic 5G waveforms and calculating EVM, but also overcoming design challenges that affect poor EVM.
Who should attend? RF designers in the Wireless, Aerospace/Defense, and Automotive industries, as well as their Managers and Communications System Architects will benefit from this presentation.
12:30 p.m. – 1:00 p.m. Eastern Time
Ambient IoT: The Journey Towards Connecting Trillions of Things
Eric Casavant
Ambient IoT was established with an ambitious mission: to tackle society’s most pressing challenges by seamlessly connecting trillions of devices to the internet using small, low cost IoT tags. Already, hundreds of millions of these tiny IoT tags have been made, automating food safety, carbon monitoring, supply chain optimization, and enhancing consumer experiences.
At the core of Ambient IoT’s value proposition is maintenance-free operation and continuous communication. To achieve this goal, these devices are often designed to be battery-less, instead relying on energy harvesting, and communicate through pre-existing channels. Therefore, the effectiveness of Ambient IoT hinges on the robustness of energy and communication networks.
To support this rapidly growing ecosystem, key standards bodies such as 3GPP for cellular, IEEE for hardware infrastructure, and Bluetooth SIG for IoT connectivity are actively shaping the standards to support mass adoption. This presentation will explore the unique approaches and strengths of each ecosystem within the context of Ambient IoT. We will outline how these standards complement and compete with each other, while also highlighting the growing opportunities in this rapidly evolving landscape.
1:00 p.m. – 1:30 p.m. Eastern Time
Impairing a 5G Non-Terrestrial Network Using a Real-Time Satellite Link Emulator
Bob Muro
5G non-terrestrial networks (NTN) are the latest technology designed to enable a 5G terrestrial or low-altitude device to communicate with non-terrestrial satellites or airborne base stations. These networks will augment existing 5G terrestrial systems, particularly in areas unsuitable for traditional base station deployment due to geographic challenges, such as open ocean or large, unpopulated desert regions.
A major design challenge for these networks is the proper evaluation of electromagnetic and environmental effects on the signal path, including noise, Doppler shift, latency, and multi-path and fading issues, all within a laboratory environment. The explosive growth of low-Earth orbit (LEO) satellites has intensified the need for a flexible, COTS satellite link emulation (SLE) system to accurately emulate the wireless path before satellite deployment. The physical layer is the starting point for the entire radio system, and recent additions of 5G technology for NTN have increased demand for these test capabilities.
This webinar will review 5G NTN basics and the value of using a COTS SLE to model the effect of naturally occurring disturbances that can affect your communications link.
1:30 p.m. – 2:00 p.m. Eastern Time
The Dawn of 5G Advanced
Chris Pearson
As we embark on the era of 5G-Advanced, the telecommunications landscape is witnessing rapid network deployments and a burgeoning subscriber base. That success is underpinned by the crucial interplay of advanced technologies, and the need for efficient spectrum allocation and harmonized 3GPP standards. The success of 5G-Advanced hinges on key factors including robust infrastructure, innovative service offerings, and a collaborative ecosystem supported by proactive regulatory processes. As we delve into this transformative phase, it’s imperative to foster regulatory environments that encourage fair competition, innovation, and equitable access to next-generation connectivity for all.
2:00 p.m. – 2:30 p.m. Eastern Time
Wi-Fi 7 Testing Challenges
James Rankin
Wi-Fi 7 brings in exciting new technologies to address challenges in today’s environment; including higher application demands e.g. Extended Reality (XR), increasing client numbers and interference. We will review those technologies, how they increase demands on the Access Point intelligence, and the increased complexity of testing especially with the new Multi-Link Operation (MLO).
April 24: PCB/Interconnect/EMC-EMI Sessions
May 22: 5G-6G/Wi-Fi/IoT Sessions
August 21: SI/PI Sessions
October 23: Radar/Automotive/SATCOM Sessions
PCB/Interconnect/EMC-EMI – April 24, 2024
10:00 a.m. – 10:30 a.m. Eastern Time
KEYNOTE: The Road from 1Gbps-NRZ to 224Gbps-PAM4
Augusto Panella
Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR capability of the chips.
As we move through the speed grades, the physical layer design of PCBs, cables assemblies, and connectors evolves. The latest data throughput and latency-driven signaling updates challenge previously acceptable design trade-offs. We’ll review interconnect design progression from 1Gbps transmission line data rates to the 224Gbps rates to highlight the on-going refinement of design goals.
10:30 a.m. – 11:00 a.m. Eastern Time
FEATURED TALK: How to Navigate Chiplet Design Complexities with Electronic Design Automation
Tim Wag-Lee
The massification of high-computational applications, such as Artificial Intelligence (AI), is steering the semiconductor industry from monolithic to chiplet-based design architectures. In this new design philosophy, various chip functions once housed within a single large die are now segregated into modular smaller dies, called chiplets, that can be combined in a larger system. Chiplets offer improved scalability, flexibility, and cost-effectiveness but pose new challenges, especially in terms of die-to-die (D2D) communication and system management. This presentation discusses the chiplet-based design workflow and how Electronic Design Automation (EDA) tools can help overcome these challenges.
11:00 a.m. – 11:30 a.m. Eastern Time
Visualization of PCB Via Breakouts for Layout and Crosstalk Control
Scott McMorrow
Signal integrity engineers are rarely skilled at the art of layout, often designing “optimized” via breakouts that are tough, if not impossible to route in a layout environment. On the other hand, layout artists are good at their craft of insuring that all signals are routed and meet manufacturing requirements, but rarely consider signal integrity requirements. Since signal integrity engineers often make the job of layout more difficult with their fancy designs, and humongous antipad openings, it is our responsibility to at least make the process less painful for all involved. This session shows how to use a free tool that can easily visualize via breakouts for arrays of high performance signals, so that several constraints are met simultaneously:
- Acceptable insertion loss, return loss and impedance control
- Acceptable routing ability in the layout preferred direction
- And the ability to enhance the design with additional crosstalk guarding ground vias
11:30 a.m. – 12:00 p.m. Eastern Time
Mitigating EMC Risks Early – Before the First Prototype
Marek Jableka and Gilad Shapira
EMC challenges are often uncovered late in product development, leading to major delays and expenses. Identifying EMC risks early is critical for companies today.
This presentation will explore modern EDA solutions that support the design process. Attendees will learn techniques to spot design choices prone to EMC issues without a prototype. Finding these risks early allows quick, low-cost mitigation. The focus will be on practical methods and tools usable by both electronics and layout designers in their daily workflows, without requiring deep EMC expertise. We’ll also prioritize solutions that yield rapid results.
We’ll demonstrate solutions for verifying schematics and harnessing the power of modern AI/ML-based analysis against component datasheets. Discover techniques to tackle EMC challenges in PCB design and delve into PCB verifications paired with a simulation-driven approach, unveiling strategies for addressing power and signal integrity concerns.
12:30 p.m. – 1:00 p.m. Eastern Time
Things Not Seen on the Schematic
Patrick G. André
With the best intentions to have a great design that will pass EMI testing, the results are at times disappointing. The reasons are often not well understood, and the solutions are a mystery. The reasons for this can be related to the parasitic issues of the components and layout. These issues and techniques on how to avoid them will be discussed.
1:00 p.m. – 1:30 p.m. Eastern Time
Near Field EMI Measurement & Simulation Correlation for Mixed Reality Rigid Flex Designs
Kundan Chand, Raul Stavoli and Pedro El Awar
One of the major design challenges for MR/VR devices is to meet electromagnetic interference and compatibility (EMI/EMC) standards while also implementing high density routing in small form factors. It is critical to capture these issues early in the design cycle to minimize design iterations and to have more flexibility with routing, component placement, etc. This workshop introduces a novel approach to modeling EMI/EMC analysis with a simulation flow that targets a system comprising complex packages (PKGs) and rigid-flex PCBs (RFPCs), which are designed for MR/VR applications. Using Cadence’s Clarity 3D Solver, near-field distribution caused by high-speed clock (CLK) signals will be extracted. The modeling includes cross-hatched planes, multiple stackups, and current excitations. In addition, the challenges faced while correlating EMI for various bending angles of the RFPC will be shared. Excellent correlation between simulated and measured data will be demonstrated when comparing the H-near fields in near-field tests. The presented EMI/EMC simulation flow will enable engineers to pinpoint potential EMI/EMC issues via the field propagation throughout the system and simplify the challenge of meeting EMI/EMC compliance for designers.
1:30 p.m. – 2:00 p.m. Eastern Time
Empowering Careers in Electronics: Navigating Interconnects and PCB’s
Tara Dunn
Uncover the pivotal role of networking and continuous education in the dynamic world of electronics interconnects and printed circuit boards (PCBs). Explore the profound impact of training initiatives on career advancement and job performance, emphasizing the need for professionals to leverage available educational opportunities. Understand the relationship between industry and workforce development, shedding light on how the flourishing electronics sector propels career growth and is attracting a new generation to electronics manufacturing. Addressing current industry trends, the talk will spotlight the top technical topics capturing attention. Join us to discover the keys to success in this rapidly evolving field.
5G-6G/Wi-Fi/IoT Sessions
10:00 a.m. – 10:30 a.m. Eastern Time
KEYNOTE: Towards an AI-native Air Interface for 6G
Andreas Roessler
Machine learning (ML) has achieved tremendous success in a wide range of applications, such as image and video recognition, object detection and natural language processing. Over the last few years, researchers and key industry players have been investigating the native support of AI/ML-based models and algorithms for signal processing in the future 6G air interface. The initial focus will be on the receiver part as the concept of a neural receiver is introduced. Simulations show a performance gain compared to traditional concepts, but open questions remain about computational complexity, power consumption and lifecycle management.
10:30 a.m. – 11:00 a.m. Eastern Time
FEATURED TALK: Multiphysics Modeling of High-Speed Communication Devices
Andrew Strikwerda
In this session, we will explore the use of the finite element method (FEM) for multiphysics modeling in high-speed communication technologies, such as phased antenna arrays and 5G millimeter-wave filters. The performance of microwave and millimeter-wave antennas and circuits is pivotal for 5G, the internet of things (IoT), and satellite communications. By employing electromagnetic simulation software to assess these devices before physical fabrication and testing, the design process can be streamlined significantly, saving both time and effort throughout the development cycle.
We will introduce an efficient modeling workflow for microwave and millimeter-wave devices and demonstrate how to incorporate additional physical phenomena such as electromagnetic heating. The session will conclude with a comprehensive overview of the advantages of multiphysics couplings that account for heating, mechanical deformations, and other physical effects.
11:00 a.m. – 11:30 a.m. Eastern Time
Key Insights from Ericsson Microwave Outlook
Mikael Öhberg
The introduction of 5G has seen E-band spread to most parts of the world, in this the 10th edition of the report, we see that the E-band spectrum fulfills the capacity needs for most deployments even beyond 2030. Driven by advancements in microwave technology, the antenna toolbox has expanded to provide diverse options and possibilities. Operational costs for managing a microwave network can be significantly reduced by applying network automation. To find out more about this and other interesting topics, download Ericsson Microwave Outlook 2023. In this year’s edition we continue providing insights and trends up until 2030 in the wireless backhaul industry.
11:30 a.m. – 12:00 p.m. Eastern Time
Solve RF Design Challenges to Achieve Low EVM with 5G Modulation
Daren McClearnon
Digitally modulated 5G signals demand wider bandwidth and higher linearity from RF transceiver circuits, which then require more advanced design techniques. However, many RF designers continue to design using only CW signal in their design software, which leads to ambiguity about the true design margin of their components, and the effectiveness of their design approaches. Error vector magnitude (EVM) has emerged as the key figure of merit for circuit design and optimization, going beyond traditional analog measures such as P1dB and IP3. It’s well known in measurement equipment, but how to apply it effectively and inexpensively in simulation, as a design tool?
This webinar will highlight a variety of practical simulation techniques for not only creating realistic 5G waveforms and calculating EVM, but also overcoming design challenges that affect poor EVM.
Who should attend? RF designers in the Wireless, Aerospace/Defense, and Automotive industries, as well as their Managers and Communications System Architects will benefit from this presentation.
12:30 p.m. – 1:00 p.m. Eastern Time
Ambient IoT: The Journey Towards Connecting Trillions of Things
Eric Casavant
Ambient IoT was established with an ambitious mission: to tackle society’s most pressing challenges by seamlessly connecting trillions of devices to the internet using small, low cost IoT tags. Already, hundreds of millions of these tiny IoT tags have been made, automating food safety, carbon monitoring, supply chain optimization, and enhancing consumer experiences.
At the core of Ambient IoT’s value proposition is maintenance-free operation and continuous communication. To achieve this goal, these devices are often designed to be battery-less, instead relying on energy harvesting, and communicate through pre-existing channels. Therefore, the effectiveness of Ambient IoT hinges on the robustness of energy and communication networks.
To support this rapidly growing ecosystem, key standards bodies such as 3GPP for cellular, IEEE for hardware infrastructure, and Bluetooth SIG for IoT connectivity are actively shaping the standards to support mass adoption. This presentation will explore the unique approaches and strengths of each ecosystem within the context of Ambient IoT. We will outline how these standards complement and compete with each other, while also highlighting the growing opportunities in this rapidly evolving landscape.
1:00 p.m. – 1:30 p.m. Eastern Time
Impairing a 5G Non-Terrestrial Network Using a Real-Time Satellite Link Emulator
Bob Muro
5G non-terrestrial networks (NTN) are the latest technology designed to enable a 5G terrestrial or low-altitude device to communicate with non-terrestrial satellites or airborne base stations. These networks will augment existing 5G terrestrial systems, particularly in areas unsuitable for traditional base station deployment due to geographic challenges, such as open ocean or large, unpopulated desert regions.
A major design challenge for these networks is the proper evaluation of electromagnetic and environmental effects on the signal path, including noise, Doppler shift, latency, and multi-path and fading issues, all within a laboratory environment. The explosive growth of low-Earth orbit (LEO) satellites has intensified the need for a flexible, COTS satellite link emulation (SLE) system to accurately emulate the wireless path before satellite deployment. The physical layer is the starting point for the entire radio system, and recent additions of 5G technology for NTN have increased demand for these test capabilities.
This webinar will review 5G NTN basics and the value of using a COTS SLE to model the effect of naturally occurring disturbances that can affect your communications link.
1:30 p.m. – 2:00 p.m. Eastern Time
The Dawn of 5G Advanced
Chris Pearson
As we embark on the era of 5G-Advanced, the telecommunications landscape is witnessing rapid network deployments and a burgeoning subscriber base. That success is underpinned by the crucial interplay of advanced technologies, and the need for efficient spectrum allocation and harmonized 3GPP standards. The success of 5G-Advanced hinges on key factors including robust infrastructure, innovative service offerings, and a collaborative ecosystem supported by proactive regulatory processes. As we delve into this transformative phase, it’s imperative to foster regulatory environments that encourage fair competition, innovation, and equitable access to next-generation connectivity for all.
2:00 p.m. – 2:30 p.m. Eastern Time
Wi-Fi 7 Testing Challenges
James Rankin
Wi-Fi 7 brings in exciting new technologies to address challenges in today’s environment; including higher application demands e.g. Extended Reality (XR), increasing client numbers and interference. We will review those technologies, how they increase demands on the Access Point intelligence, and the increased complexity of testing especially with the new Multi-Link Operation (MLO).
August 21: SI/PI Sessions
10:00 a.m. – 10:30 a.m. Eastern Time
KEYNOTE: Free SIPI Tools Every Engineer Needs
Prof Eric Bogatin
You are not going to design a 224 Gbps system using a free tool, but you may gain insight into how to solve a problem at 224 Gbps using a free tool. I will share my top five favorite free SIPI tools, which I think every engineer needs to have to help them accelerate up the learning curve. These include S-parameter viewers, 2D field solvers, 3D field solvers, and circuit simulators. I might even throw in a bonus tool or two.
10:30 a.m. – 11:00 a.m. Eastern Time
FEATURED TALK: The Challenges of Designing 224G PAM4 Interconnects
Jignesh Shah
The explosion of computing combined with the slowing down of Moore’s Law has brought a need for high-density, high-speed, short-reach interconnectivity between chipsets running at 224G PAM4. Doubling the data rate, doubling the number of I/O, as well as increased signal integrity and thermal challenges, makes interconnect design a critical part of the overall system architecture. In this talk, we will discuss the evolution of interconnects over the past decade and the challenges and solutions when designing 224G PAM4 passive interconnects for datacenter, AI and HPC applications.
11:00 a.m. – 11:30 a.m. Eastern Time
Design and Analysis Challenges as Chips Transform Into 3D Systems
John Park
As the electronics industry begins to pivot from Moore’s Law to “More-than-Moore,” we are witnessing a convergence of technologies across ICs and systems design. This fundamental shift in how we design today’s products requires new advanced design and analysis flows that combine tools across the spectrum of EDA solutions. One of the most critical capabilities of these system-level designs and flows is to enable seamless cross-domain co-design and co-analysis, allowing engineers to achieve the highest performance and lowest cost products. The days of IC and package designers ‘throwing data over the wall’ are over. Heterogeneous Integration (HI) is ushering in a new era of electronic product design with collaboration at its core – one that lives or dies on the seamless interaction between analog/digital IC teams, package design teams and the electrical/thermal characterization/analysis teams, that need to validate these complex 3D systems.
The use of advanced packaging technologies to combine smaller, discrete chiplets into one system-in-package (SiP) not only pushes the need for more advanced multi-die packaging but it also makes packaging part and parcel of the process. Doing so significantly reduces dependence on Moore’s Law at a time when building advanced monolithic system-on-chip (SoC) is no longer the best option from a cost and technology perspective.
This presentation will describe the challenges engineering teams face when pivoting from monolithic SoC design to 3D multi-die/chiplet package design and how EDA can help in addresses these challenges.
11:30 a.m. – 12:00 p.m. Eastern Time
Demonstrating Simulation-Measurement Correlation to 50GHz and Beyond
John Phillips and Alfred P. Neves
While working with a host of customers this last year we continue to hear “simulation-measurement is a bit of a black art,” or “no, we don’t really close the loop on our high-speed design process,” or “we thought our measurements were really good, no we have not questioned that…,” etc.
Senior veterans from Cadence and Wild River Technology (WRT) have teamed up the last two years to address fundamental problems of practical electromagnetics using the Cadence Clarity 3D EM Solver and the WRT CMP-50 Advanced Channel Modeling Platform signal integrity tool. This webinar highlights this effort and covers topics such as the influence of measurements techniques and fabrication on the physical side and boundary conditions and material identification for simulations. Whether de-embedding measurements ensure good simulation to measurement correspondence will be discussed, as well as other options. An endemic little-known issue is measurements, which will be discussed in terms of correspondence. The webinar will conclude with guidelines to improve physical measurements and recommendations to ensure correlated Clarity EM simulations. This discussion is relevant to all folks using a host of EDA tools and test hardware.
12:30 p.m. – 1:00 p.m. Eastern Time
The Intersection of Signal Integrity and Electromagnetic Compatibility
Joseph C. (Jay) Diepenbrock
Signal Integrity (SI) and Electromagnetic Compatibility (EMC) have traditionally been thought of as separate fields of engineering. However, as the speed of high speed interfaces increase, many of the parameters of interest have become increasingly common to both fields. This talk will discuss some of those parameters and how problems in one field can bleed over into the other and cause problems there. They include impedance discontinuities, rise/fall time, skew, crosstalk, plane splits, return paths, and cable shield termination.
1:00 p.m. – 1:30 p.m. Eastern Time
How to Fully Verify SerDes-based Designs Before Prototype Manufacture
Todd Westerhoff
“Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible, problems creep into layouts that cause issues during lab testing and result in costly, time-consuming respins.
Why is that? We maintain there are two big contributors:
- We often don’t simulate what we actually build
- We don’t verify ALL our serial channels– we only analyze a few
In this presentation, we’ll dig into these two issues and show you how to address them:
- We’ll discuss how small details of board fabrication (e.g. off-the-shelf vs. pressed prepreg thickness) can significantly impact design performance. We’ll show why it’s critical to model a board as it will be manufactured – instead of how you wish it could be manufactured.
- We’ll discuss post-layout verification and how to verify operating design margins for ALL of your serial channels, instead of just a select few. We’ll discuss what it takes to create an automated analysis methodology and how it can be coupled with Protocol Compliance Analysis (e.g. PCIe-5) to assess your design’s operating margins.
1:30 p.m. – 2:00 p.m. Eastern Time
Correcting Ground Loop Errors in Multi-Channel Oscilloscope Measurements with Power Rail and other Single-Ended Probes
Benjamin Dannan
Power rail probes are hugely popular for measuring voltage noise. As core current increases and voltage falls the margins get smaller. Placing more than one probe, in different locations on the printed circuit board (PCB), will add ground loop noise to your measurements. This is true for power rail probes, but also for all single ended voltage probes. Multi-channel oscilloscopes have become ubiquitous solutions to support voltage noise measurements in multiple power domain applications. When acquiring signals and making low-noise measurements, engineers often focus on the oscilloscope’s key features, such as bandwidth and dynamic range. However, as voltage compliance requirements become more stringent, understanding the noise impact of our ground loop from our probing solutions is critical, especially when assessing voltage ripple in power systems.
Unfortunately, ground loops are common in real-world measurement setups and pose a significant challenge when performing multi-channel measurements on the same Device Under Test (DUT). These ground loops introduce additional noise errors into measurement results, rendering even high-bandwidth oscilloscopes and expensive probing solutions ineffective. This presentation will show how to mitigate the impacts of ground loop by adding a coaxial isolator to significantly improve measurement accuracy. The isolator improves the CMRR performance of the probes, greatly improving the accuracy of multi-channel oscilloscope measurements using power rail probes and other single-ended probing solutions.
Addressing ground loop errors is paramount for achieving reliable, accurate multi-channel measurements. Engineers must be aware of these challenges and take appropriate steps to mitigate their impact on measurement accuracy.