Addressing the Data Transfer Disconnect Between the RF Design Platform and the PCB Layout Editor

RF/microwave IP, developed in a specialized design environment, must be transferred to a PCB layout editor where manufacturing constraints, design rule checking (DRC), layout vs. schematic (LVS) and corporate-approved components can be applied and integrated with the power and digital electronics.  The transfer of RF design data (schematic and layout) is tyopically re-entered manually by the layout team using information provided by the RF team, wasting considerable time and effort. New workflow interoperability between the Cadence AWR Design Environment and Allegro PCB editor platforms enables RF and layout teams to share data more efficiently to reduce design turnaround times and potential errors. This talk will present the new RF-to-PCB workflow enabled by the Cadence Unified Library and will highlight how design teams can use this capability to greatly improve efficiency and time to market.